This invention relates to a method for driving an image display device including scan electrodes arranged in a matrix-like manner and a unit therefor, and more particularly to such a method and a unit which are suitably applied to an image display device having field-emission cathodes incorporated therein.
When an electric field which is set to be about 10.sup.9 (V/m) is applied to a surface of a metal material or that of a semiconductor material, a tunnel effect permits electrons to pass through a barrier, resulting in the electrons being discharged to a vacuum even at a normal temperature. Such a phenomenon is referred to as "field emission" and a cathode constructed so as to emit electrons based on such a principle is referred to as "field emission cathode".
Recent development of semiconductor processing techniques permits a field emission cathode elements of a size as small as microns to be produced. This results in a field emission cathode of the surface emission type being made of an array of the field emission cathode elements thus produced, so that research and development of an image display device using the field emission cathode have been made.
Now, a field emission cathode (hereinafter also referred to as "FEC") commonly called a Spindt-type prepared by semiconductor processing techniques will be described hereinafter as an example of a conventional field emission cathode with reference to FIG. 4. The conventional field emission cathode includes a substrate 100 made of glass or the like, on which cathode electrodes 102 are formed of metal such as aluminum or the like by deposition. The cathode electrodes 102 each are formed thereon with emitters 104 of a conical shape, each of which may be made of metal such as molybdenum or the like.
The cathode electrodes 102 each are formed on a portion thereof which is not provided with the emitters 104 with a film 106 of silicon dioxide (SiO.sub.2), which is then formed thereon with a gate 108. The gate 108 and SiO.sub.2 film 106 are formed with a plurality of through-holes 110 of a circular shape in cross section in a manner to be common to both.
Such construction results in the emitters 104 being arranged so as to be exposed via the through-holes 110 while being supported on the cathode electrode 102, respectively.
The emitters 104 of a conical shape are arranged so as to be spaced from each other at pitches as small as 10 microns or less, so that a large number of emitters or tens of thousands to hundreds of thousands of emitters may be mounted on one substrate. Also, the conventional field emission cathode permits a distance between the gate and a distal end of each of the emitters to be as small as less than 1 micron, so that application of a voltage V.sub.GC as low as only tens of volts between the gate 108 and the emitters 104 may permit the emitters to field-emit electrons therefrom. The electrons thus field-emitted from the emitters 104 are captured by an anode 112 arranged at a predetermined interval above the gate 108 and having a positive voltage V.sub.A applied thereto.
Characteristics between an anode current Ia of the conventional FEC thus constructed and a gate-cathode voltage V.sub.GC thereof are shown in FIG. 5. As shown in FIG. 5, as the gate-cathode voltage V.sub.GC is gradually increased, the anode current I.sub.a starts to flow to the anode 112. The voltage V.sub.GC at which the anode current Ia starts to flow thereto is referred to as a threshold voltage V.sub.TH, which causes an electric field between the gate 108 and the cathode 102 to be about 10.sup.9 V/m, resulting in electrons starting to be emitted from the emitters 104, so that the anode current Ia starts to flow to the anode 112. In general, a voltage of about V.sub.OP shown in FIG. 5 which is considerably higher than the threshold voltage V.sub.TH is applied between the gate 108 and the cathode 102, during which the anode current I.sub.OP is permitted to flow to the anode 112.
The anode current derived from each one of the emitters 104 of a conical shape is at a micro-level. In view of the fact, the conventional FEC arranges a plurality of emitters in a manner like an array, to thereby increase the anode current to a desired level.
In this instance, formation of phosphors on the anode 112 results in electrons field-emitted from the emitters 104 impinging on the phosphors during capture of the electrons by the anode, leading to luminescence of the phosphors. Application of such a principle to a display device leads to realization of an image display device having an FEC incorporated therein (hereinafter also referred to as "FED").
Such an FED may be driven by such a drive unit constructed as shown in FIG. 6 by way of example and adapted to carry out operation as shown in FIG. 2.
More particularly, the drive unit, as shown in FIG. 6, includes a shift register 20 which has gate data and clocks (CLK) for shift inputted thereto. The shift register 20 then feeds the gate data to gate drivers 21-1 to 21-n in order. The gate data applied to the gate drivers 21-1 to 21-n have such sequence pulses as indicated at GT1 to GTn in FIG. 2, which are generated at a cycle nT, wherein T indicates a pulse width of each of the pulses.
Each of the gate drivers 21-1 to 21-n may be constructed of a driver IC or the like and has transistors Tr1 and Tr2 connected thereto to provide a push-pull circuit, so that gate electrodes 22-1 to 22-n each may be driven at an increased speed. The transistor Tr1 has a drive power supply V.sub.G connected to a terminal of a source thereof, and the transistor Tr2 has a bias power supply V.sub.S connected to a terminal of a source thereof so that each of the gate electrodes 22-1 to 22-n may be driven at a reduced swing voltage.
The gate electrodes 22-1 to 22-n each are formed into a stripe-like manner, wherein the gate driver 21-1 is adapted to drive the gate electrode 22-1, the gate driver 21-2 drives the gate electrode 22-2,--and subsequently the last gate driver 21-n drives the last gate electrode 22-n. Thus, supposing that gate data are applied to the gate driver 21-1, resulting in the gate driver 21-1 being selected, the transistor Tr1 of the gate driver 21-1 is caused to be turned on to apply the voltages V.sub.G +V.sub.S to the gate electrode 22-1, leading to the driving of the gate electrode 22-1.
Then, when the gate data are transferred from the gate driver 21-1 to the next gate driver 21-2 to render the gate driver 21-1 nonselected, the transistors Tr1 and Tr2 of the gate driver 21-1 are turned off and turned on, respectively, so that the gate electrode 22-1 may be kept at a bias voltage V.sub.S.
The bias voltage V.sub.S is set at a level of the threshold voltage V.sub.TH between the gate and the cathode or below.
A shift register 23 has serial cathode data inputted thereto, which are converted into parallel cathode data in the register 23 and then latched in a latch circuit 24. For this purpose, the shift register 23 has clocks (CLK) for shift inputted thereto. The cathode data thus latched in the latch circuit 24 are fed to cathode drivers 25-1 to 25-m, respectively. The cathode data fed to the cathode drivers 25-1 to 25-m serve as such image data of a cycle T as indicated at C1 to Cm to FIG. 2.
Cathode electrodes 26-1 to 26-m each are formed into a stripe-like shape and driven by the cathode drivers 25-1 to 25-m in order, respectively.
The gate electrodes 22-1 to 22-n and cathode electrodes 26-1 to 26-m are arranged so as to define a matrix by cooperation with each other. The cathode electrodes 26-1 to 26-m are provided on portions thereof positionally corresponding to intersections between the gate electrodes 22-1 to 22-n and the cathode electrodes 26-1 to 26-m with emitter arrays E.sub.11, E.sub.12, - - - , E.sub.21, E.sub.22, - - - , E.sub.nm, which constitute picture cells for the image display device.
Thus, when the gate drivers 21-1 to 21-n are selected in order and the gate electrodes 22-1 to 22-n are driven in order, a voltage of a predetermined level is applied between the gate electrodes and the cathode electrodes to permit electrons to be emitted from the emitter arrays, which electrons are then captured by the anode arranged apart upwardly from the the gate electrodes 22-1 to 22-n.
Then, the electrons thus emitted from the emitter arrays are caused to impinge on the phosphors deposited on the anode, leading to luminescence of the phosphors. At this time, the image data are kept applied to the cathode electrodes 26-1 to 26-m as described above, so that luminescence of the phosphors is carried out depending on the image data, to thereby provide a desired image display.
As described above, the gate drivers 21-1 to 21-n of the drive unit for the image display device have a bias voltage V.sub.S applied thereto in order to minimize the swing voltage. For example, when the gate data are transferred from the gate electrode 22-1 to the gate electrode 22-2 to render the gate driver 21-1 nonselected, the bias voltage V.sub.S is applied to the gate electrode 22-1.
However, application of the bias voltage V.sub.S to the gate electrode when the gate driver is kept nonselected causes a gate voltage charged in the gate electrode to be discharged from the gate drive power supply V.sub.G and cathode drive power supply V.sub.C, leading to occurrence of a reactive power.
In view of the problem, it is proposed to ground each of the gate electrodes once during non-selection of each of the gate drivers and then keep the gate electrode at an increased impedance, leading to electrical isolation of the gate electrode.
In this instance, the transistors Tr1 and Tr2 of each of the gate drivers 21-1 to 21-n shown in FIG. 6 are driven independently from each other and, for example, the terminal of the source of the transistor Tr2 is grounded.
Thus, when a scan pulse is applied to, for example, the gate driver 21-1 as shown in (a) of FIG. 7, the transistors Tr1 and Tr2 of the gate driver 21-1 are turned on and turned off, respectively, so that the gate electrode 22-1 is applied thereto a voltage Vg, resulting in being driven.
Then, when the scan pulse is transferred from the gate driver 21-1 to the gate driver 21-2 to render the gate driver 21-2 nonselected, the transistor Tr1 of the gate driver 21-1 is turned off and the transistor Tr2 of the gate driver 21-1 is applied thereto a reset pulse for a predetermined period of time T as shown in (b) of FIG. 7, resulting in the gate electrode 22-1 being grounded as indicated at GND in FIG. 7. Then, the transistor Tr2 is turned off to keep the gate electrode 22-1 at a high impedance as indicated at Z in FIG. 7.
In this instance, the gate electrode is grounded once during a period of time (one-frame period) before it is selected again and kept at the high impedance Z during the remaining period of time, so that a current path is formed during only the period R for which the resent pulse is applied, to thereby reduce a reactive current. However, this, as shown in (c) of FIG. 7, causes an off-state voltage (.DELTA.V) of the gate electrode to be gradually increased due to leakage of a voltage from the cathode electrode during the high impedance period. An increase in off-state voltage above the threshold voltage V.sub.TH causes luminescent spots to occur on an image plane, to thereby deteriorate quality of display of the image display device.
Further, the conventional image display device is constructed so as not to apply the bias voltage V.sub.S to each of the gate drivers, to thereby provide a margin for the leakage voltage. Unfortunately, this causes the gate voltage to be equal to the swing voltage, to thereby cause the swing voltage to be increased by about 20 to 30 volts as compared with application of bias voltage V.sub.S, leading to an increase in power consumption.